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dual 3 mhz, 600 ma buck regulator with 150 ma ldo adp5022 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2010 analog devices, inc. all rights reserved. features input voltage range: 2.4 v to 5.5 v tiny 16-ball, 2 mm 2 mm wlcsp package overcurrent and thermal protection soft start factory programmable undervoltage lockout on vdda system supply of either 2.2 v or 3.9 v factory programmable default output voltages for all 3 channels buck1 and buck2 key specifications current mode architecture for excellent transient response 3 mhz operating frequency uses tiny multilayer inductors and capacitors forced pwm and auto pwm/psm modes out-of-phase operation for reduced input filtering 100% duty cycle low dropout mode 24 a typical quiescent current per channel, no switching ldo key specifications stable with 1 f ceramic output capacitors high psrr 60 db up to 10 khz low output noise 65 v rms output noise at vout3 = 3.3 v low dropout voltage: 150 mv @ 150 ma load 11 a typical ground current at no load applications usb devices handheld products multivoltage power for processors, asics, fpgas, and rf chipsets general description the adp5022 is a micro power management unit (micro pmu) that combines two high performance buck regulators and a low dropout regulator (ldo) in a tiny 16-ball 2.08 mm 2.08 mm wlcsp to meet demanding performance and board space requirements. the high switching frequency of the buck regulators enables tiny multilayer external components and minimizes the board space required. when the mode pin is set high, the buck reg- ulators operate in forced pwm mode. when the mode pin is set low, the buck regulators automatically switch operating modes, depending on the load current level. at higher output loads, the buck regulators operate in pwm mode. when the load current falls below a predefined threshold, the regulators operate in power save mode (psm), improving the light-load efficiency. the two bucks operate out-of-phase to reduce the input capacitor requirement and noise. the low quiescent current, low dropout voltage, and wide input voltage range of the adp5022 ldo extends the battery life of portable devices. the ldo maintains power supply rejection greater than 60 db for frequencies as high as 10 khz while operating with a low headroom voltage. each regulator in the adp5022 has a dedicated, independent enable pin. a high voltage level applied to the enable pin activates the respective regulator. the default output voltages are factory programmable and can be set to a wide range of options. c2 4.7f c3 4.7f vin1 vin3 en1 on off pwm pwm/psm v in = 2.4v to 5.5v sw1 vout1 pgnd1 mode c4 10f c6 1f v out1 @ 600ma l1 1h l2 1h en_bk1 buck1 mode c1 1f vin2 en2 vdda on off sw2 vout2 vout3 agnd pgnd2 c5 10f v out2 @ 600ma en_bk2 buck2 mode en3 on off v out3 @ 150ma en_ldo1 ldo1 adp5022 08253-001 inductor inductor c1 l1 cout_1 cout_2 cout_3 c2 c4 c3 08253-061 4.7mm 5.0mm figure 1. typical applications circuit figure 2. typical pcb layout
adp5022 rev. c | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 buck1 and buck2 specifications................................................. 4 ldo specifications ...................................................................... 5 absolute maximum ratings............................................................ 6 thermal data ................................................................................ 6 thermal resistance ...................................................................... 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 16 power management unit........................................................... 16 buck section................................................................................ 17 ldo section ............................................................................... 18 applications information .............................................................. 19 buck external component selection....................................... 19 ldo capacitor selection .......................................................... 20 pcb layout guidelines.................................................................. 22 evaluation board schematics and artwork ................................ 23 suggested layout ........................................................................ 23 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 10/10rev. b to rev. c c hanges to figure 2.......................................................................... 1 changes to table 9.......................................................................... 20 6/10rev. a to rev. b changes to ordering guide .......................................................... 25 11/09revision a: initial version
adp5022 rev. c | page 3 of 28 specifications vdda = vin1 = vin2 = 3.6 v, vin3 = (vout3 + 0.5 v) or 2.4 v, whichever is greater, vin3 vin1, t j = ?40c to +125c, unless otherwise noted. 1 table 1. parameter symbol test conditions/comments min typ max unit input voltage range system and buck input supplies voltage range v dda , v in1 , and v in2 low uvlo level models 2.4 5.5 v high uvlo level models 4.5 5.5 v ldo input supply voltage range v in3 2.3 5.5 v shutdown current i gnd-sd en1 = en2 = en3 = gnd 0.5 a en1 = en2 = en3 = gnd t j = ?40c to +85c 2 a thermal shutdown thermal shutdown threshold tsd th t j rising 150 c thermal shutdown hysteresis tsd hys 20 c en1, en2, en3, mode inputs en1, en2, en3, mode input logic high v ih vdda = vin1 = vin2 1.2 v en1, en2, en3, mode input logic low v il vdda = vin1 = vin2 0.4 v en1, en2, en3, mode input leakage current v i-leakage pin at (vdda = vin1 = vin2) or gnd 0.05 1 a standby current all channels enabled, no load i stby 80 a all channels enabled, no load, no buck switching i stby-nosw 59 85 a vin3 undervoltage lockout input voltage rising uvlo vin3rise 2.20 v input voltage falling uvlo vin3fall 1.45 v vdda undervoltage lockout input voltage rising uvlo vddarise high uvlo level (factory programmed) 4.15 v low uvlo level (factory programmed) 2.35 v input voltage falling uvlo vddafall high uvlo level (factory programmed) 3.40 v low uvlo level (factory programmed) 2.00 v 1 all limits at temperature extremes are guaranteed via co rrelation using standard st atistical quality control.
adp5022 rev. c | page 4 of 28 buck1 and buck2 specifications vdda = vin1 = vin2 = 3.6 v, vin3 = (vout3 + 0.5 v) or 2.4 v, whichever is greater, vin3 vin1, t j = ?40c to +125c, unless otherwise noted. 1 table 2. parameter symbol test conditions/comments min typ max unit operating supply current buck1 only i gnd1 i load1 = 0 ma, device not switching, en1 = vdda, en2 = en3 = gnd 24 a buck2 only i gnd2 i load2 = 0 ma, device not switching, en2 = vdda, en1 = en3 = gnd 32 a buck1 and buck2 only i gnd1-2 i load1 = i load1 = 0 ma, device not switch- ing, en1 = en2 = vdda, en3 = gnd 48 64 a output voltage accuracy v out1 , v out2 pwm mode, vin1 = vin2 = 2.4 v to 5.5 v, i load1 = i load2 = 0 ma ? 600 ma ?3 +3 % power save mode to pwm current threshold i psm-pwm 105 ma pwm to power save mode current threshold i pwm-psm 100 ma sw characteristics, buck1 and buck2 pfet on resistance r pfet typical at vin1 = vin2 = 3.6 v 165 275 m typical at vin1 = vin2 = 5.0 v 125 m nfet on resistance r nfet typical at vin1 = vin2 = 3.6 v 125 220 m typical at vin1 = vin2 = 5.0 v 100 m current limit i limit1 , i limit2 pfet switch peak current limit 750 950 1050 ma oscillator frequency f sw 2.5 3.0 3.5 mhz start-up time 2 from shutdown state t startup12-sd 250 s 1 all limits at temperature extremes are guaranteed via co rrelation using standard st atistical quality control. 2 start-up time is defined as the time from a rising edge on en1/en2 to vout1/vout2 reaching 90% of their nominal value.
adp5022 rev. c | page 5 of 28 ldo specifications vdda = vin1 = vin2 = 3.6 v, vin3 = (vout3 + 0.5 v) or 2.3 v, whichever is greater, vin3 vin1, i out3 = 10 ma; c in3 = c out3 = 1 f, t j = ?40c to +125c, unless otherwise noted. 1 table 3. parameter symbol test conditions/comments min typ max unit operating supply current 2 i vin3-gnd i out3 = 0 a 11 21 a i out3 = 10 ma 16 29 a i out3 = 150 ma 31 43 a output voltage accuracy v out3 100 a < i out3 < 150 ma, vin3 = (vout3 + 0.5 v) to 5.5 v ?2 +2 % regulation line regulation ?vout3/?v in3 vin3 = (vout3 + 0.5 v) to 5.5 v, i out = 1 ma ?0.03 +0.03 %/ v load regulation 3 ?vout3/?i out3 i out3 = 1 ma to 150 ma 0.002 0.0075 %/ma dropout voltage 4 v dropout vout3 = 3.0 v, i out3 = 10 ma 7 mv vout3 = 3.0 v, i out3 = 150 ma 110 150 mv start-up time 5 from shutdown state t startup3-sd 200 s current-limit threshold 6 i limit3 160 240 350 ma output noise out noise 10 hz to 100 khz, vin3 = 5 v, vout3 = 3.3 v 65 v rms 10 hz to 100 khz, vin3= 5 v, vout3 = 2.4 v 52 v rms 10 hz to 100 khz, vin3 = 5 v, vout3 = 1.2 v 40 v rms power supply rejection ratio psrr 10 khz, vin3 = 5 v, vout3 = 3.3 v 60 db 10 khz, vin3 = 5 v, vout3 = 2.3 v 66 db 10 khz, vin3 = 5 v, vout3 = 1.2 v 70 db 1 all limits at temperature extremes are guaranteed via co rrelation using standard st atistical quality control. 2 ldo operating supply current is the current drawn from vin3 to agnd when the ldo is enabled. whenever any regulator channel is enabled, current is drawn from vin1 to agnd. this current is 8 a typical and is in cluded in the i gnd1 , i gnd2 , and i gnd1-2 specifications. 3 based on an en d-point calculation using 1 ma and 150 ma loads. 4 dropout voltage is defined as the input-to-output voltage differe ntial when the input voltage is set to the nominal output vol tage. this applies only for output voltages above 2.3 v. 5 start-up time is defined as the time between the rising edge of en3 to vout3 being at 90% of its nominal value. 6 current-limit threshold is defi ned as the current at which vout3 drops to 90% of the specified typica l value. for example, the current limit for a 3.0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 v or 2.7 v.
adp5022 rev. c | page 6 of 28 absolute maximum ratings table 4. parameter rating vdda, vin1, vin2, vin3, vout1, vout2, vout3, en1, en2, en3, mode to gnd ?0.3 v to +6 v storage temperature range ?65c to +150c operating junction temperature range ?40c to +125c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp5022 can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature (t a ) does not guarantee that the junction temperature (t j ) is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature may exceed the maximum limit as long as the junction temperature is within specification limits. t j of the device is dependent on t a , the power dissipation (p d ) of the device, and the junction-to-ambient thermal resistance ( ja ) of the package. maximum t j is calculated from t a and p d using the following formula: t j = t a + ( p d ja ) ja of the package is based on modeling and calculation using a 4-layer board. the junction-to-ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and envi- ronmental conditions. the specified values of ja are based on a 4-layer, 4 3 circuit board. refer to jedec jesd 51-9 for detailed information on the board construction. for additional information, see the an-617 application note, microcsp tm wafer le vel chip s cale package . thermal resistance ja is specified for the worst-case conditions, that is, a device soldered on a circuit board. table 5. thermal resistance package type ja unit 16-ball, 0.5 mm pitch wlcsp 65 c/w esd caution
adp5022 rev. c | page 7 of 28 pin configuration and fu nction descriptions top view (ball side down) not to scale 08253-002 1 a b c d 234 ball a 1 indicator vout3 vin1 sw1 pgnd1 vin3 en2 mode vout2 vdda vin2 sw2 pgnd2 agnd en1 en3 vout1 figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic description a1 vout3 ldo output voltage and sensing input. a2 agnd analog ground. a3 vin3 ldo input supply (vin3 vin1 = vin2 = vdda). a4 vdda supply input for the hous ekeeping block and uvlo sensing. b1 vin1 buck1 input supply (vin1 = vin2 = vdda). b2 en1 buck1 activation. set en1 = high: turn on buck1. set en1 = low: turn off buck1. b3 en2 buck2 activation. set en2 = high: turn on buck2. set en2 = low: turn off buck2. b4 vin2 buck2 input supply (vin2 = vin1 = vdda). c1 sw1 buck1 switching node. c2 en3 ldo activation. set en3 = high: turn on ldo. en3 = low: turn off ldo. c3 mode buck1/buck2 operating mode: mode = high: forc ed pwm operation. mode = low: auto pwm/psm operation. c4 sw2 buck2 switching node. d1 pgnd1 dedicated power ground for buck1. d2 vout1 buck1 output voltage sensing input. d3 vout2 buck2 output voltage sensing input. d4 pgnd2 dedicated power ground for buck2.
adp5022 rev. c | page 8 of 28 typical performance characteristics vin1 = vin2 = vin3 = vdda = 5.0 v, t a = 25c, unless otherwise noted. 08253-023 2 3 t 1 ch1 2.00v m 200s a ch1 1.92v t 45.40% b w ch2 2.00v b w ch3 2.00v b w vout1 vout2 vout3 figure 4. 3-channel start-up waveforms, vin3 cascaded from vout1 0.00010 0.00008 0.00006 0.00004 0.00002 0 2.82.62.4 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 v in (v) i in a (a) 08253-064 figure 5. system quiescent current vs. input voltage, vout1 = 0.8 v, vout2 = 2.5 v, vin3 = vout2, vout3 = 1.2 v, all channels unloaded 08253-021 4 1 3 t 2 ch1 2.00v ch4 5.00v m 40.0s a ch3 2.2v t 11.20% b w ch2 50.0ma ? b w b w ch3 5.00v b w sw vout en i in figure 6. buck1 startup, vout1 = 3.3 v, i out1 = 10 ma 08253-020 4 1 3 t 2 ch1 2.00v ch4 5.00v m 40.0s a ch3 2.2v t 11.20% b w ch2 50.0ma ? b w b w ch3 5.00v b w sw vout en i in figure 7. buck2 startup, vout2 = 1.8 v, i out2 = 5 ma 0.06 0.07 0.08 0.09 0.10 0.11 0.12 0.13 0.14 0.15 2.4 2.9 3.4 3.9 4.4 4.9 5.4 output current (a) input voltage (v) pwm to psm psm to pwm 08253-067 figure 8. buck 2 psm to pwm transition, vout2 = 1.8 v 3.354 3.334 3.314 3.294 3.274 3.254 3.234 0 0.1 0.2 0.3 0.4 0.6 i out (a) v out a (v) 08253-058 0.5 t a = +25c t a = ?40c t a = +85c figure 9. buck1 load regulation across temperature, vout1 = 3.3 v, auto mode
adp5022 rev. c | page 9 of 28 1.834 1.824 1.814 1.804 1.794 1.784 1.774 1.764 0 0.1 0.2 0.3 0.4 0.6 i out (a) v out b (v) 08253-057 0.5 t a = +25c t a = ?40c t a = +85c figure 10. buck2 load regulation across temperature, vout2 = 1.8 v, auto mode 1.834 1.824 1.814 1.804 1.794 1.784 1.774 1.764 0 0.1 0.2 0.3 0.4 0.6 0.5 i out (a) v out b (v) 08253-054 v in = 5.5v v in = 4.5v v in = 3.6v v in = 2.4v figure 11. buck 2 load regulation across input voltage, vout1 = 1.8 v, pwm mode 3.354 3.334 3.314 3.294 3.274 3.254 3.234 0 0.1 0.2 0.3 0.4 0.6 0.5 i out (a) v out a (v) 08253-055 v in = 3.6v v in = 4.5v v in = 5.5v figure 12. buck1 load regulation across input voltage, vout2 = 3.3 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 i out (a) efficiency (%) 08253-038 v in = 3.6v v in = 4.5v v in = 5.5v figure 13. buck1 efficiency vs. load current, across input voltage, vout1 = 3.3 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) 08253-039 v in = 3.6v v in = 4.5v v in = 5.5v figure 14. buck1 efficiency vs. load current, across input voltage, vout1 = 3.3 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 i out (a) efficiency (%) 08253-036 v in = 5.5v v in = 4.5v v in = 3.6v v in = 2.4v figure 15. buck2 efficiency vs. load current, across input voltage, vout2 = 1.8 v, auto mode
adp5022 rev. c | page 10 of 28 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) 08253-035 v in = 5.5v v in = 4.5v v in = 3.6v v in = 2.4v figure 16. buck2 efficiency vs. load current, across input voltage, vout2 = 1.8 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 i out (a) efficiency (%) 08253-034 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v figure 17. buck1 efficiency vs. load current, across input voltage, vout1 = 0.8 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.001 0.01 0.1 1 i out (a) efficiency (%) 08253-065 v in = 2.4v v in = 3.6v v in = 4.5v v in = 5.5v figure 18. buck1 efficiency vs. load current, across input voltage, vout1 = 0.8 v, pwm mode 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 i out (a) efficiency (%) 08253-062 t a = ?40c t a = +25c t a = +85c figure 19. buck1 efficiency vs. load current, across temperature, vout1 = 3.3 v, auto mode 100 90 80 70 60 50 40 30 20 10 0 0.0001 0.001 0.01 0.1 1 i out (a) efficiency (%) 08253-063 t a = +25c t a = ?40c t a = +85c figure 20. buck2 efficiency vs. load current, across temperature, vout2 = 1.8 v, auto mode 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 0 0.1 0.2 0.3 0.4 0.6 0.5 output current (a) frequency (mhz) 08253-040 t a = +25c t a = ?40c t a = +85c figure 21. buck2 switching frequency vs. output current, across temperature, vout2 = 1.8 v, pwm mode
adp5022 rev. c | page 11 of 28 08253-025 2 4 t 1 ch1 50.0v m 4.00s a ch2 240ma t 28.40% b w ch2 500ma ? ch4 2.00v b w i sw vout sw figure 22. typical waveforms, vout1 = 3.3 v, i out1 = 30 ma, auto mode 08253-024 2 4 t 1 ch1 50.0v m 4.00s a ch2 220ma t 28.40% b w ch2 500ma ? ch4 2.00v b w i sw vout sw figure 23. typical waveforms, vout2 = 1.8 v, i out2 = 30 ma, auto mode 08253-027 2 4 t 1 ch1 50mv m 400ns a ch2 220ma t 28.40% b w ch2 500ma ? ch4 2.00v b w i sw vout sw figure 24. typical waveforms, vout1 = 3.3 v, i out1 = 30 ma, pwm mode 08253-026 2 4 t 1 ch1 50mv m 400ns a ch2 220ma t 28.40% b w ch2 500ma ? ch4 2.00v b w i sw vout sw figure 25. typical waveforms, vout2 = 1.8 v, i out2 = 30 ma, pwm mode 08253-012 ch1 50.0mv ch3 1.00v ch4 2.00v m 1.00ms a ch3 4.80v 1 3 t 30.40% t b w b w b w vout vin sw figure 26. buck1 response to line tr ansient, input voltage from 4.5 v to 5.0 v, vout1 = 3.3 v, pwm mode 08253-013 1 4 t 3 ch1 50.0mv ch3 1.00v ch4 2.00v m 1.00ms a ch3 4.80v t 30.40% b w b w b w vout vin sw figure 27. buck2 response to line transient, v in = 4.5 v to 5.0 v, vout2 = 1.8 v, pwm mode
adp5022 rev. c | page 12 of 28 08253-016 4 1 t 2 ch1 50.0mv ch4 5.00v m 20.0s a ch2 356ma t 60.000s b w ch2 50.0ma ? b w b w vout i out sw figure 28. buck1 response to load transient, i out1 from 1 ma to 50 ma, vout1 = 3.3 v, auto mode 08253-015 4 1 t 2 ch1 50.0mv ch4 5.00v m 20.0s a ch2 379ma t 22.20% b w ch2 50.0ma ? b w b w vout i out sw figure 29. buck2 response to load transient, i out2 from 1 ma to 50 ma, vout2 = 1.8 v, auto mode 08253-017 4 2 t 1 ch1 50.0mv ch4 5.00v m 20.0s a ch2 408ma t 20.40% b w ch2 200ma ? b w b w vout i out sw figure 30. buck1 response to load transient, i out1 from 20 ma to 180 ma, vout1 = 3.3 v, auto mode 08253-018 4 2 t 1 ch1 100mv ch4 5.00v m 20.0s a ch2 88.0ma t 19.20% b w ch2 200ma ? b w b w vout i out sw figure 31. buck2 response to load transient, i out2 from 20 ma to 180 ma, vout2 = 1.8 v, auto mode 08253-066 4 1 3 t 2 ch1 5.00v ch4 5.00v m 400ns a ch4 1.90v t 50.00% b w ch2 5.00v b w b w ch3 5.00v b w vout1 vout2 sw1 sw2 figure 32. vout and sw waveforms for buck1 and buck2 in pwm mode showing out-of-phase operation 08253-022 2 3 t 1 ch1 2.00v m 40.0s a ch3 2.2v t 11.20% b w ch2 50.0ma ? b w b w ch3 5.00v b w vout en i in figure 33. ldo startup, vout3 = 3.0 v, i out3 = 5 ma
adp5022 rev. c | page 13 of 28 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 i out (a) v out c (v) 08253-046 2.780 2.785 2.790 2.795 2.800 2.805 2.810 2.815 2.820 v in = 3.3v v in = 4.5v v in = 5.0v v in = 5.5v figure 34. ldo load regulation across input voltage, vout3 = 2.8 v 2.85 2.84 2.83 2.82 2.81 2.80 2.79 2.78 2.77 2.76 2.75 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 i out (a) v out c (v) 08253-049 t a = ?40c t a = +25c t a = +85c figure 35. ldo load regulation across temperature, vin3 = 3.3 v, vout3 = 2.8 v 3.0 2.5 2.0 1.5 1.0 0.5 0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 v in (v) v out c (v) 08253-045 i out = 150ma i out = 100ma i out = 10ma i out = 1ma i out = 100a figure 36. ldo line regulation across output load, vout3 = 2.8 v 50 45 40 35 30 25 20 15 10 5 0 3.3 3.8 4.3 4.8 5.3 input voltage (v) ground current (a) 08253-043 150ma 100ma 10ma 1ma 100a 1a figure 37. ldo ground current vs. input voltage, across output load, vout3 = 2.8 v 50 45 40 35 30 25 20 15 10 5 0 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 load current (a) ground current (a) 08253-044 figure 38. ldo ground current vs. output load, vin3 = 3.3 v, vout3 = 2.8 v 3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 i out (a) v out a (v) 08253-030 v in = 3.6v v in = 4.5v v in = 5.5v figure 39. ldo current capability across input voltage, vout3 = 2.8 v
adp5022 rev. c | page 14 of 28 08253-019 2 t 1 ch1 100mv m 40.0s a ch2 52.0ma t 19.20% b w ch2 100ma ? b w vout i out figure 40. ldo response to load transient, i out3 from 1 ma to 80 ma, vout3 = 2.8 v 08253-014 2 3 t 1 ch1 20.0mv ch3 1.00v m 100s a ch3 4.80v t 28.40% b w b w vout vin figure 41. ldo response to line transient, input voltage from 4.5 v to 5.5 v, vout3 = 2.8 v 60 55 50 45 40 35 30 25 0.001 0.01 0.1 1 10 100 i load (ma) rms noise (v) 08253-047 3.3vin 5vin figure 42. ldo output noise vs. load current, across input voltage, vout3 = 2.8 v 60 65 55 50 45 40 35 30 25 0.001 0.01 0.1 1 10 100 i load (ma) rms noise (v) 08253-048 5vin 3.3vin figure 43. ldo output noise vs. load current, across input voltage, vout3 = 3.0 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08253-050 100a 1ma 10ma 50ma 100ma 150ma figure 44. ldo psrr across output load, vin3 = 3.3 v, vout3 = 2.8 v 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08253-051 100a 1ma 10ma 50ma 100ma 150ma figure 45. ldo psrr across output load, vin3 = 3.3 v, vout3 = 3.0 v
adp5022 rev. c | page 15 of 28 0 ?20 ?40 ?60 ?80 ?100 ?120 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08253-053 100a 1ma 10ma 50ma 100ma 150ma figure 46. ldo psrr across output load, vin3 = 5.0 v, vout3 = 2.8 v 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) 08253-052 100a 1ma 10ma 50ma 100ma 150ma figure 47. ldo psrr across output load, vin3 = 5.0 v, vout3 = 3.0 v
adp5022 rev. c | page 16 of 28 theory of operation enable control ldo control ldo undervoltage lock out soft start pwm/ psm control buck2 driver and antishoot through soft start pwm/ psm control buck1 driver and antishoot through oscillator thermal shutdown system undervoltage lock out pwm comp gm error amp gm error amp psm comp psm comp low current i limit pwm comp low current i limit r1 r2 adp5022 v out1 v out2 vin1 sw1 pgnd1 en1 en2 en3 vdda vin3 agnd vout3 mode pgnd2 08253-003 sw2 vin2 figure 48. functional block diagram power management unit the adp5022 is a micro power management units (micro pmu) combining two step-down (buck) dc-to-dc converters and a single low dropout linear regulator (ldo). the high switching frequency and tiny 16-ball wlcsp package allow for a small power management solution. to combine these high performance converters and regulators into the micro pmu, there is a system controller allowing them to operate together. each regulator has a dedicated enable pin. en1 controls the activation for buck1, en2 controls the activation for buck2, and en3 controls the activation of the ldo. logic high applied to the enx pin turns on the regulator, and a logic low applied to the enx pin turns off the regulator. when a regulator is turned on, the output voltage is controlled through a soft start circuit to avoid a large inrush current due to the discharged output capacitors. the buck regulators can operate in forced pwm mode if the mode pin is at a logic high level. in forced pwm mode, the switching frequency of the two bucks is always constant and does not change with the load current. if the mode pin is at a logic low level, the switching regulators operate in an auto pwm/ psm mode. in this mode, the regulators operate at fixed pwm frequency when the load current is above the power saving current threshold. when the load current falls below the power saving current threshold, the regulator in question enters power saving mode where the switching occurs in bursts. the burst repetition is a function of the current load and the output capacitor value. this operating mode reduces the switching and quiescent current losses. the auto pwm/psm mode transition is controlled independently for each buck regulator. the two bucks operate synchronized to each other.
adp5022 rev. c | page 17 of 28 thermal protection in the event that the junction temperature rises above 150c, the thermal shutdown circuit turns off the converters and the ldo. extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. a 20c hysteresis is included so that when thermal shutdown occurs, the bucks and ldo do not return to opera- tion until the on-chip temperature drops below 130c. when coming out of thermal shutdown, soft start is initiated. undervoltage lockout to protect against battery discharge, undervoltage lockout (uvlo) circuitry is integrated in the system. if the input voltage on vdda drops below a typical 2.15 v uvlo threshold, all channels shut down. in the buck channels, both the power switch and the synchronous rectifier turn off. when the voltage on vdda rises above the uvlo threshold, the part is enabled once more. alternatively, the user can select device models with a uvlo set at a higher level, suitable for usb applications. for these models, the device hits the turn-off threshold when the input supply drops to 3.65 v typical. enable/shutdown when all three enable pins are held low, the device is in shutdown mode, and the input current remains below 2 a. buck section the two bucks use a fixed frequency and high speed current mode architecture. the bucks operate with an input voltage of 2.4 v to 5.5 v. control scheme the bucks operate with a fixed frequency, current mode pwm control architecture at medium to high loads for high efficiency but shift to a power save mode (psm) control scheme at light loads to lower the regulation power losses. when operating in fixed frequency pwm mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. when operating in psm at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. during part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency. pwm mode in pwm mode, the bucks operate at a fixed frequency of 3 mhz set by an internal oscillator. at the start of each oscillator cycle, the pfet switch is turned on, sending a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the pfet switch and turns on the nfet synchronous rectifier. this sends a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle. the buck regulates the output voltage by adjusting the peak inductor current threshold. power save mode (psm) the bucks smoothly transition to psm operation when the load current decreases below the psm current threshold. when either of the bucks enter power save mode, an offset is induced in the pwm regulation level, which makes the output voltage rise. when the output voltage reaches a level approximately 1.5% above the pwm regulation level, pwm operation is turned off. at this point, both power switches are off, and the buck enters an idle mode. the output capacitor discharges until the output voltage falls to the pwm regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. this process is repeated while the load current is below the psm current threshold. psm current threshold the psm current threshold is set to 100 ma. the bucks employ a scheme that enables this current to remain accurately con- trolled, independent of input and output voltage levels. this scheme also ensures that there is very little hysteresis between the psm current threshold for entry to and exit from the psm. the psm current threshold is optimized for excellent efficiency over all load currents. oscillator/phasing of inductor switching the adp5022 ensures that both bucks operate at the same switching frequency when both bucks are in pwm mode. additionally, the adp5022 ensures that when both bucks are in pwm mode, they operate out-of-phase, whereby the buck2 pfet starts conducting exactly half a clock period after the buck1 pfet starts conducting.
adp5022 rev. c | page 18 of 28 enable/shutdown the bucks start operation with soft start when the en1 or en2 pin is toggled from logic low to logic high. pulling the en1 or en2 pin low disables that channel. short-circuit protection the bucks include frequency foldback to prevent output current runaway on a hard short. when the voltage at the feedback pin falls below half the target output voltage, indicating the possi- bility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. the reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current. soft start the bucks have an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter. current limit each buck has protection circuitry to limit the amount of positive current flowing through the pfet switch and the amount of negative current flowing through the synchronous rectifier. the positive current limit on the power switch limits the amount of current that can flow from the input to the output. the negative current limit prevents the inductor current from reversing direction and flowing out of the load. 100% duty operation with a drop in input voltage or with an increase in load current, the buck may reach a limit where, even with the pfet switch on 100% of the time, the output voltage drops below the desired output voltage. at this limit, the buck transitions to a mode where the pfet switch stays on 100% of the time. when the input conditions change again and the required duty cycle falls, the buck immediately restarts pwm regulation without allowing overshoot on the output voltage. this is particularly useful in battery-powered applications to achieve the longest operation time by taking full advantage of the whole battery voltage range. maintaining regulation is dependent on the input voltage, load current, and output voltage. this can be calculated from the following equation: v in(min) = v out(max) + i load(max) ( r ds(on)max + r l ) where: v out(max) is the nominal output voltage plus the maximum tolerance. i load(max) is the maximum load current plus inductor ripple current. r ds(on)max is the maximum p-channel switch r ds(on) . r l is the dc resistance of the inductor. ldo section the ldo is a low quiescent current, low dropout linear regulator and provides up to 150 ma of output current. drawing a low 30 a quiescent current (typical) at full load makes the ldo ideal for battery-operated portable equipment. the ldo operates with an input voltage of 2.3 v to 5.5 v. it also provides high power supply rejection ratio (psrr), low output noise, and excellent line and load transient response with just a small 1 f ceramic input and output capacitor. internally, the ldo consists of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transistor. output current is delivered via the pmos pass device, which is con- trolled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to flow and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, reducing the current flowing to the output. ldo undervoltage lockout the adp5022 integrates an undervoltage lockout function on the vin3 input voltage, which ensures that the ldo output drive is disabled whenever vin3 is below a threshold of approximately 2.0 v. where the adp5022 is configured to supply vin3 from either vout1 or vout2, this ensures that the ldo powers up safely in this cascaded configuration.
adp5022 rev. c | page 19 of 28 applications information buck external component selection trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in figure 1 . inductor the high switching frequency of the adp5022 bucks allows for the selection of small chip inductors. for best performance, use inductor values between 0.7 h and 3 h. suggested inductors are shown in table 7 . the peak-to-peak inductor current ripple is calculated using the following equation: lfv vvv i sw in out in out ripple ? = ) ( where: f sw is the switching frequency. l is the inductor value. the minimum dc current rating of the inductor must be greater than the inductor peak current. the inductor peak current is calculated using the following equation: 2 )( ripple max load peak i ii + = inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (dcr). larger sized inductors have smaller dcr, which may decrease inductor conduction losses. inductor core losses are related to the magnetic permeability of the core material. because the bucks are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low emi. table 7. suggested 1.0 h inductors vendor model dimensions (mm) i sat (ma) dcr (m) murata lqm2mpn1r0ng0b 2.0 1.6 0.9 1400 85 murata lqm18fn1r0m00b 1.6 0.8 0.8 150 26 taiyo yuden cbmf1608t1r0m 1.6 0.8 0.8 290 90 coilcraft epl2014-102ml 2.0 2.0 1.4 900 59 tdk glfr1608t1r0m-lr 1.6 0.8 0.8 230 80 coilcraft 0603ls-102 1.8 1.69 1.1 400 81 toko mdt2520-cn 2.5 2.0 1.2 1350 85 output capacitor higher output capacitor values reduce the output voltage ripple and improve load transient response. when choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. ceramic capacitors are manufactured with a variety of dielec- trics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recom- mended for best performance. y5v and z5u dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calcu- lated using the following equation: c eff = c out (1 ? tempco ) (1 ? tol) where: c eff is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c out is 9.2481 f at 1.8 v, as shown in figure 49 . substituting these values in the equation yields c eff = 9.2481 f (1 ? 0.15) (1 ? 0.1) = 7.0747 f to guarantee the performance of the bucks, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. 0 2 4 6 8 10 12 0123456 08253-004 dc bias voltage (v) capacitance (f) figure 49. typical capacitor performance
adp5022 rev. c | page 20 of 28 the peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: () out sw in ripple clf v v = 2 2 out sw ripple cf i = 8 capacitors with lower equivalent series resistance (esr) are preferred to guarantee low output voltage ripple, as shown in the following equation: rippl e ripple cout i v esr the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 f and a maximum of 40 f. table 8. suggested 10 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j106 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 tdk x5r c1608jb0j106k 0603 6.3 panasonic x5r ecj1vb0j106m 0603 6.3 the buck regulators require 10 f output capacitors to guar- antee stability and response to rapid load variations and to transition in and out the pwm/psm modes. in certain applications, where one or both buck regulator powers a processor, the operating state is known because it is con- trolled by software. in this condition, the processor can drive the mode pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 f to 4.7 f because the regulator does not expect a large load variation when working in psm mode, see figure 50 . sw1 vin1 vin2 en1 en2 en3 vdda vin3 vout1 pgnd1 mode vout3 l1 1h c4 4.7f sw2 vout2 pgnd2 l2 1h c5 4.7f c6 1f c2 4.7f c3 4.7f c1 1f v in 2 .5v to 5.5v activation inputs always on micro pmu adp5022 processor analog sub-system vcore gpio vio vana 08253-005 figure 50. processor system power management with psm/pwm control input capacitor higher value input capacitors help to reduce the input voltage ripple and improve transient response. maximum input capa- citor current is calculated using the following equation: in out in out max load cin v vvv ii ) ( )( ? to minimize supply noise, place the input capacitor as close to the vin pin of the buck as possible. as with the output capacitor, a low esr capacitor is recommended. the effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 f and a maximum of 10 f. a list of suggested capacitors is shown in table 9 . table 9. suggested 4.7 f capacitors vendor type model case size voltage rating (v) murata x5r grm188r60j475me19d 0603 6.3 taiyo yuden x5r jmk107bj475 0603 6.3 panasonic x5r ecj-0eb0j475m 0402 6.3 ldo capacitor selection output capacitor the adp5022 ldo is designed for operation with small, space- saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with the esr value. the esr of the output capacitor affects stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 or less is recommended to ensure stability of the adp5022. transient response to changes in load current is also affected by output capacitance. using a larger value of output capacit- ance improves the transient response of the adp5022 to large changes in load current. input bypass capacitor connecting a 1 f capacitor from vin3 to gnd reduces the circuit sensitivity to printed circuit board (pcb) layout, especially when long input traces or high source impedance are encountered. if greater than 1 f of output capacitance is required, increase the input capacitor to match it. table 10. suggested 1.0 f capacitors vendor type model case size voltage rating (v) murata x5r grm155b30j105k 0402 6.3 tdk x5r c1005jb0j105kt 0402 6.3 panasonic x5r ecj0eb0j105k 0402 6.3 taiyo yuden x5r lmk105bj105mv-f 0402 10.0
adp5022 rev. c | page 21 of 28 input and output capacitor properties use the following equation to determine the worst-case capa- citance accounting for capacitor variation over temperature, component tolerance, and voltage. use any good quality ceramic capacitors with the adp5022 as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v or 10 v are recommended for best performance. y5v and z5u dielectrics are not recommended for use with any ldo because of their poor temperature and dc bias characteristics. c eff = c bias (1 ? tempco ) (1 ? tol ) where: c bias is the effective capacitance at the operating voltage. tempco is the worst-case capacitor temperature coefficient. tol is the worst-case component tolerance. in this example, the worst-case temperature coefficient (tempco) over ?40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10% and c bias is 0.94 f at 1.8 v as shown in figure 51 . figure 51 depicts the capacitance vs. voltage bias characteristic of a 0402 1 f, 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature variation of the x5r dielectric is about 15% over the ?40c to +85c tempera- ture range and is not a function of package or voltage rating. substituting these values into the following equation. c eff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over temperature and tolerance at the chosen output voltage. to guarantee the performance of the adp5022, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors are evaluated for each application. 1.2 1.0 0.8 0.6 0.4 0.2 0 012345 dc bias voltage (v) capacitance (f) 08253-006 6 figure 51. capacitance vs. voltage characteristic
adp5022 rev. c | page 22 of 28 pcb layout guidelines poor layout can affect adp5022 performance, causing electro- magnetic interference (emi) and electromagnetic compatibility (emc) problems, ground bounce, and voltage losses. poor layout can also affect regulation and stability. a good layout is implemented using the following guidelines: ? place the inductor, input capacitor, and output capacitor close to the ic using short tracks. these components carry high switching frequencies, and large tracks act as antennas. ? route the output voltage path away from the inductor and sw node to minimize noise and magnetic interference. ? maximize the size of ground metal on the component side to help with thermal dissipation. ? use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.
adp5022 rev. c | page 23 of 28 evaluation board schematics and artwork a1 d4 d3 c4 d1 d2 c1 vin1 vin2 vdda sw1 b1 b4 r1 0 ? r2 0 ? a4 a3 a2 c3 b2 b3 c2 vout1 pgnd1 sw2 vout2 pgnd2 vout3 vin3 agnd mode en1 en2 c out _2 0603 10f c3 0603 4.7f c1 0402 1f c2 0603 4.7f c out _3 0402 1f en3 ldo j8 j9 j10 j13 j12 j11 buck2 l1 1h l2 1h buck1 c out _1 0603 10f j1 j2 j3 j4 j5 j7 j6 08253-007 figure 52. evaluation board schematic suggested layout 0 8253-008 figure 53. top layer, recommended layout 08253-009 figure 54. second layer, recommended layout
adp5022 rev. c | page 24 of 28 08253-010 figure 55. third layer, recommended layout 08253-011 figure 56. bottom layer, recommended layout
adp5022 rev. c | page 25 of 28 outline dimensions 013009-b a b c d 0.660 0.602 0.544 2.12 2.08 sq 2.04 0.380 0.352 0.324 1 2 3 4 bottom view (ball side up) top view (ball side down) 0.280 0.250 0.220 0.330 0.310 0.290 ball 1 identifier seating plane 0.04 nom coplanarity 0.50 ref 0.022 ref 1.50 ref figure 57. 16-ball wafer level chip scale package [wlcsp] back-coating included (cb-16-7) dimensions shown in millimeters ordering guide model 1 output voltage (v) 2 undervoltage lockout level temperature range package description package option branding code ADP5022ACBZ-1-R7 vout1 = 3.3 v vout2 = 1.5 v vout3 = 1.8 v low ?40c to +125c 16-ball wafer level chip scale package [wlcsp] cb-16-7 l9h adp5022acbz-2-r7 vout1 = 1.2 v vout2 = 1.8 v vout3 = 2.8 v low ?40c to +125c 16-ball wafer level chip scale package [wlcsp] cb-16-7 l9j adp5022acbz-4-r7 vout1 = 3.3 v vout2 = 1.8 v vout3 = 3.3 v high ?40c to +125c 16-ball wafer level chip scale package [wlcsp] cb-16-7 lg7 adp5022acbz-6-r7 vout1 = 1.0 v vout2 = 1.8 v vout3 = 2.5 v low ?40c to +125c 16-ball wafer level chip scale package [wlcsp] cb-16-7 lh5 1 z = rohs compliant part. 2 for additional voltage options, contact a local sales or distribution representative . additional output voltages and uvlo available are buck1 and buck2: 3.3 v, 3.0 v, 2.8 v, 2.5 v, 2.3 v, 2.0 v, 1.82 v, 1.8 v, 1.6 v, 1.5 v, 1.3 v, 1.2 v, 1.1 v, 1.0 v, 0.9 v, 0.8 v ldo: 3.3 v, 3.0 v, 2.9 v, 2.8 v, 2.775 v, 2.5 v, 2.0 v, 1.875 v, 1.8 v, 1.75 v, 1.7 v, 1.65 v, 1.6 v, 1.55 v, 1.5 v, 1.2 v uvlo: 2.25 v or 3.9 v
adp5022 rev. c | page 26 of 28 notes
adp5022 rev. c | page 27 of 28 notes
adp5022 rev. c | page 28 of 28 notes ?2009C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08253-0-10/10(c)

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